1. Field of the Invention
The present invention relates to adjustment of analog signal outputted from an analog signal generating section of an internal power source circuit or the like incorporated in a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which interface for input-output signals is achieved by digital signal and adjustment method of the semiconductor integrated circuit device.
2. Description of Related Art
FIG. 17 shows an internal power source circuit 300 incorporated in a semiconductor integrated circuit device, a fuse circuit 400 for adjusting the voltage of an internal power source voltage VII, and a decoding circuit 600 as circuit examples based on conventional technology. The internal power source circuit 300 is constituted of a non-inverting amplification circuit employing an operational amplifier circuit. If a gate voltage of a PMOS transistor MP1 is controlled by an output signal of the operational amplifier circuit, a reference voltage VREF inputted from a reference terminal REF, which is an inverting input terminal, is subjected to non-inverting amplification so as to generate the internal power source voltage VII. An amplification rate at this time is determined by selecting resistance elements R, R0-R3 connected to a path from the output terminal of the internal power source voltage VII to the non-inverting input terminal VAF of the operational amplifier circuit. This selection is performed by supplying electricity to any one of transfer gates S0-S3 connected between the respective resistance elements R, R0-R3.
This selection is carried out by the decoding circuit 600. The decoding circuit 600 decodes predetermined signals FS<0>, <1> stored in the fuse circuit 400 and selects any one of decoding signals D<0>-D<3>. Two-phase signals of in-phase and anti-phase for each of the predetermined signals FS<0>, <1> are generated and logical add operation is executed by combining the respective signals so as to obtain the decoding signal D<0>-<3>.
The fuse circuit 400 is constituted of a resistance element and a fuse element and stores predetermined signals FS<0>, <1> for outputting a predetermined internal power source voltage VII. The fuse element is not cut out when a low level signal is stored and the fuse element is cut out when a high level signal is stored. In the semiconductor integrated circuit, individual device characteristics vary because of characteristic variation due to manufacturing reason and generally, the reference voltage VREF inputted to the reference terminal REF also varies. The predetermined signals FS<0>, <1> are signals for correcting this variation so as to output the predetermined internal power source voltage VII and is set up for each internal power source circuit 300. This setting work is called trimming work and carried out according to a test flow shown in FIG. 18.
In the test flow of FIG. 18, the internal power source voltage VII is measured with a tester device, which is an external device of the semiconductor integrated circuit. Because the fuse element is not cut out at this stage, the predetermined signals FS<0>, <1> are low level signals. A transfer gate S0 is selected in the internal power source circuit 300 so as to set up a minimum amplification rate. How the amplification rate of the internal power source circuit 300 should be changed can be calculated preliminarily based on a measured voltage value of the internal power source voltage VII. That is, a fuse element which should be cut out is predetermined depending on a difference between an initially measured voltage value of the internal power source voltage VII and the predetermined value. FIG. 18 shows a test flow for breaking a fuse element depending on the measured internal power source voltage VII.
If the initially measured internal power source voltage VII is a voltage value VIIX lower than a range adjustable by selecting the amplification rate (VII<VIIX), the semiconductor integrated circuit is a defective product. If it is over the predetermined voltage value VIIZ (VII≧VIIZ), the fuse element does not have to be cut out. If respective transfer gates S1, S2 are selected, the initially measured voltage values VII, which is to be set as the predetermined voltage value VIIZ, are assumed to be VII1, VII2. Consequently, if the initially measured voltage value VII is VIIX, VII2, VII1, VIIZ, a fuse element which should be cut out corresponding thereto is automatically determined.
According to a conventional technology, if the internal power source voltage VII in the semiconductor integrated circuit incorporating the internal power source circuit 300 is trimmed, the internal power source voltage VII needs to be measured according to a trimming test flow. Therefore, analog data which enables measurement of analog voltage needs to be used for the trimming test. If other analog circuit than the internal power source circuit 300 is loaded, the analog signal for adjustment needs to be also measured.
On the other hand, with intensification and miniaturization of semiconductor integrated circuit technology in recent years, the semiconductor integrated circuit in digital field, which is represented by system LSI, has been loaded with an analog circuit block containing analog function such as an internal power source circuit.
For the reason, the semiconductor integrated circuit, which employs digital signal as an input-output interface to an external terminal, needs to be provided with a special measuring terminal (analog terminal) for adjusting the analog signal such as the internal power source voltage, which is a problem to be solved.
More specifically, the analog circuit block, which is provided in the semiconductor integrated circuit, is disposed at an arbitrary position corresponding to semiconductor integrated circuit design. Where the analog terminal should be disposed differs depending on the design. A wiring path, wiring length, wiring load and the like from the analog circuit block to the analog terminal differ depending on the semiconductor integrated circuit design. In order to output an analog signal to the analog terminal at a high precision, a sufficient care needs to be taken to changes or the like of the analog value due to mixture of noise by digital signals from peripheral circuits block or adjacent wirings and wiring load on a wiring path for each design. Consequently, a great burden is applied to its design aspect in order to provide with a special analog terminal necessary for adjustment of the analog signal, which is a problem to be solved.
Further, with a test on the digital signal inputted/outputted into/from the digital terminal, an analog signal outputted from the analog terminal needs to be measured. That is, both digital test and analog test need to be carried out at the same time. Thus, it is necessary to prepare a tester device having both digital testing function and analog testing function. Consequently, the tester device becomes complicated and expensive, so that testing time automatically increases. Through-put from the test worsens and cost necessary for the test increases, which are problems which should be solved.
Further, the digital test and analog test need to be carried out independently and when the analog test is performed, the digital function needs to be kept in a predetermined state. For the reason, an influence upon the analog signal by the operation of the digital function cannot be tested, which is a problem to be solved.